STR720 datasheet(139/401 Pages) STMICROELECTRONICS

139 / 401 page

STR720 - RESET AND CLOCK CONTROL UNIT (RCCU)

139/401

13.3 Functional Description

The Reset and Clock Control Unit fully manages all the aspects related to reset assertion,

reset release, clock generation and configuration.

TheAPB clock domain is fully asynchronous with respect to the other clock domains. There is

a fixed timing relationship between AHB clock domain and ATAPI clock domain (ATAPI clock is

aligned on AHB falling edge) thus simplifying the logic interface between these 2 domains.

13.3.1

Reset Management

The Reset Manager generates a reset when one of the following events occurs:

A Hardware reset, initiated by a low level on the Reset pin

A Software reset, forced setting a control bit inside the RCCU

A Watchdog reset

HW reset and Watchdog reset are asynchronous: as soon as one of these Reset inputs is

driven low, a Reset cycle is initiated (see Figure 16 on page 139). When the Reset input goes

high again or a Software reset is asserted, 768 CLK plus 8 AHB_CLK cycles are counted

before exiting the reset state. (this signal is not used in STR720 device)

Figure 16. Reset timing

RESET

AHB_CLK

...

768 CYCLES

8 CYCLES

APB_CLK

ATAPI_CLK

RESET internal

CLK

STR720 数据表(PDF) 139 Page - STMicroelectronics