STR720 datasheet(141/401 Pages) STMICROELECTRONICS

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STR720 - RESET AND CLOCK CONTROL UNIT (RCCU)

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If LOCK bit return to’0’ and AUTOBYP_EN bit is set to ’1’, the system clock switches back to

PLLREFCLK disregarding PLLBYP bit value. Otherwise (i.e. AUTOBYP_EN = ’0’) the

software has to handle the system clock switching, by monitoring PLL lock and by writing a

proper bit in CLKCTL register. AUTOBYP feature can be used to avoid polling LOCK bit (or

enabling the related interrupt) during system start-up phase to automatically switch to PLL

clock once LOCK condition has been achieved.

Note

Care must be taken in using AUTOBYP feature during normal system operation,

since the sudden change of system clock frequency can lead to serial interfaces

problem. It is recommended to use this feature with particular care and keeping

LOCK related interrupts active, so to be notified about the clock change event.

When PLL block needs to be switched off, for example to reduce current consumption upon

entering a power save mode, a special sequence is required to avoid blocking the system:

1. Set PLLBYP bit at ’1’ in PLLCONF register, so to switch back system clock to PLLREF-

CLK.

2. Wait for PLLBYP_F bit in CLKFLAG register to be read back as ‘1’, to confirm that system

clock switch is completed.

3. Set PLLOFF bit at ‘1’ in PLLCONF register to safely switch off PLL block.

In case PLLOFF is set to ’1’ without observing the sequence above, system clock stops being

generated and the device hangs up to the next hardware reset event.

Whenever PLL multiplication/division factor needs to be changed, a switch-off/switch-on cycle

must be performed, following the procedures detailed in the paragraphs above.

WARNING A wrong clock selection may cause the system to stop indefinitely. In this case the

only way to start again is a hardware reset.

13.3.3

Mode of Operation

Four modes of operation are provided

13.3.3.1 Run mode

Run mode is entered when Software reset or a Hardware reset input is asserted (low) or a

Watchdog/External reset event occurs, and the entire system asynchronously enter the reset

state. RCCU reset exit status is the following:

PLL is OFF, bypassed and MX = “000111” and DX = “11”

CLK is selected as AHB clock

CLK/16 is selected as APB clock

CLK/2 is selected as ATAPI clock

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