STR720 datasheet(140/401 Pages) STMICROELECTRONICS

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STR720 - RESET AND CLOCK CONTROL UNIT (RCCU)

140/401

When RESET internal is deasserted, the RCCU enters Run mode of operation (see below).

The event causing the last Reset is flagged in the CLKFLAG register: the corresponding bit is

set. A hardware initiated reset will leave all these bits reset. The hardware reset overrides all

other conditions and forces the system to the reset state. During the Reset phase, the internal

registers are set to their reset values, where these are defined.

Note

On STR720 device, hardware reset pin has to be kept low for a duration longer than

the on-chip RC filter width (between 50 ns and 500 ns) in order to start the reset

sequence described above.

13.3.2

PLL Management

After reset the PLL is not enabled and it must be turned on and enabled by the software.

The CLK signal drives a programmable divide-by-two circuit. If the DIV2 control bit in CLK_

FLAG register is set, PLLREFCLK, is equal to CLK divided by two; if DIV2 is reset,

PLLREFCLK is identical to CLK. The divide- by- two circuit ensures also a 50% duty cycle

signal. When the PLL is active, it multiplies PLLREFCLK by a factor depending on the status

of the MX[5:0] bits in PLLCONF register. The multiplied clock is then divided, inside the PLL,

by a factor determined by the status of the DX[1:0] bits in PLLCONF register;

The PLL contains a frequency comparator between PLLREFCLK and the PLL clock output

that verifies if the PLL clock has stabilized (locked status). The bit LOCK in PLLCONF register

becomes 1 when this condition occurs and maintains this value as long as the PLL is locked,

going back to 0 if for some reason (noise on input clock line, switch off of PLL, stop and restart

of PLLREFCLK and so on) looses the programmed frequency in which it was locked. It is

possible to select the PLL clock as system clock only when the LOCK bit is ’1’ (the selection is

done by clearing PLLBYP bit).

PLL LOCK status changing is monitored by two different interrupt pending bits:

•

LOCK_I monitors PLL LOCK (0 to 1 transition of LOCK bit)

•

ULOCK_I monitors PLL UNLOCK (1 to 0 transition of LOCK bit)

System clock switching activity is monitored by DIV2_F, PLLBYP_F, IDLE_F, SLOW_F flags

inside CLKFLAG register.

In order to activate PLL to generate system clock, the following procedure is recommended:

1. Set multiplication/division factors in PLLCONF register, while PLL is still switched off.

2. Switch on PLL by resetting PLLOFF bit in PLLCONF register.

3. Wait for LOCK bit in PLL CONF register to become ‘1’ (or use related interrupt event).

4. Switch system clock to PLL output, by resetting PLLBYP bit in PLLCONF register.

Alternatively, if exact system clock frequency is not required during system set-up phase,

PLLBYP bit can be reset also immediately after resetting PLLOFF bit in PLLCONF register

(but not in the same instruction). In this way system clock is switched immediately to PLL

output, even if it has not yet settled to its final value.

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