 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STR720 数据表(PDF) 145 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STR720 数据表(HTML) 145 Page - STMicroelectronics |
|
|
145 / 401 page  STR720 - RESET AND CLOCK CONTROL UNIT (RCCU) 145/401 DIViders CONFiguration register (DIVCONF) Address Offset: 04h Reset value: 001Fh This register is write protected and can be unlocked using REG_PROT bit in SYSPROT register. Bit 15:5 = Reserved. Give ‘0’ when read and must be written to ‘0’. Bit 4:3 = Reserved. Bit 2 = ATAPI_SEL: ATAPI clock select 0: select AHB_CLK/2 as ATAPI clock 1: select AHB_CLK/3 as ATAPI clock Bit 1:0 = APB_DIV[1:0]: APB output clock divider factor. This bit field configures the A-APB clock generation. Refer to Table 38 for A-APB divider settings. 15 14 13 12 11 10 9 8 765432 1 0 Reserved Reserved ATAPI_ SEL APB_DIV[1:0] -rw rw rw rw rw Table 38. APB divider settings APB_DIV1 APB_DIV0 APB_CK 0 0 AHB_CLK/2 0 1 AHB_CLK/4 1 0 AHB_CLK/8 1 1 AHB_CLK/16 1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
