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STR720 数据表(PDF) 166 Page - STMicroelectronics |
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STR720 数据表(HTML) 166 Page - STMicroelectronics |
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166 / 401 page  STR720 - ASYNCHRONOUS AHB-APB BRIDGE (A3BRG) 166/401 Peripheral Under Reset register 0 (PUR0) Address Offset: 80h Reset value: 0000 1003h Bits 31:13 = Reserved, always read as 0. Bit 12:0 = PxxUR: Peripheral xx Under Reset with 0 ≤xx<12 When set, the PxxUR bit specifies the peripheral xx is not under reset. 0 : Peripheral xx reset line is active. 1 : Peripheral xx reset line is not active. Note Bits 0, 1 and 12 correspond to the AHB/APB bridge, the A-APB Global Control Register and the watchdog (WDG) respectively and are forced to 1 by hardware. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved - 15 14 13 12 11 10 9 8 765432 1 0 Reserved 1 P(xx)CO 1 1 - r rw rw rw rw rw rw rw rw rw rw r r 1 |
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