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STR720 数据表(PDF) 167 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 167 Page - STMicroelectronics

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STR720 - ASYNCHRONOUS AHB-APB BRIDGE (A3BRG)
167/401
Emulator Peripheral Clock Gating register 0 (EMU_PCG0)
Address Offset: A0h
Reset value: FFFF FFFFh
This register configures the status of clock gating for each of the peripherals controlled by the
bridge, while the application program execution is stopped due to a debug request. Each
peripheral can be configured to stop working as the user code reaches a breakpoint.
Bits 31:13 = Reserved, always read as 0.
Bits 12:0 = EPxxCO: Emulator Peripheral xx Clock Off with 0
≤xx<12
0: Peripheral xx clock is gated off at a debug request, regardless of the state of the
corresponding PxxCO bit in PCG0 register.
1: Peripheral xx clock gating status is unaffected by debug requests, and it is always
determined by its corresponding PxxCO bit in PCG0 register.
Table 41 shows how the status of peripheral clock depends on PCG, EMU_PCG and
ARM720 debug-mode:
Note
Bit EPCG0[0] corresponds to the AHB/APB bridge itself and is forced to 1 by
hardware.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
-
15
14
13
12
11
10
9
8
765432
1
0
Reserved
EPxxCO
1
-
rwrwrw
rw
rw
rwrwrwrw
rwrw
rw
r
Table 41. Clock Gating
PCG0
EMU_PCG0
ARM720 debug
Periph. clock
11
0
on
11
1
on
01
0
off
01
1
off
00
0
off
00
1
off
10
0
on
10
1
off
1



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