STR720 datasheet(169/401 Pages) STMICROELECTRONICS

169 / 401 page

STR720 - UART

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16 UART

16.1 Introduction

The UART interface, also referred to as the Asynchronous Serial Controller (ASC), provides

serial communication between STR720 and other microcontrollers, microprocessors or

external peripherals.

The ASC supports full-duplex asynchronous communication. Eight or nine bit data transfer,

parity generation, and the number of stop bits are programmable. Parity, framing, and overrun

error detection are provided to increase the reliability of data transfers. Transmission and

reception of data can simply be double-buffered, or 16-deep fifos may be used. For

multiprocessor communications, a mechanism to distinguish the address from the data bytes

is included. Testing is supported by a loop-back option. A 16-bit baud rate generator provides

the ASC with a separate serial clock signal.

16.2 Main Features

■

Full-duplex asynchronous communication

■

Two internal FIFOs (16 words deep) for transmit and receive data

■

16-bit baud rate generator

■

Data frames both 8 and 9 bit long

■

Parity bit (even or odd) and stop bit

■

Multiprocessor communication support

16.3 Functional Description

The ASC supports full-duplex asynchronous communication, where both the transmitter and

the receiver use the same data frame format and the same baud rate. Data is transmitted on

the TXD pin and received on the RXD pin.

16.3.1

Data frames

Eight-bit data frames (see Figure 20) either consist of:

•

eight data bits D0-7 (by setting the Mode bit field to 001);

•

seven data bits D0-6 plus an automatically generated parity bit (by setting the Mode bit

field to 011).

Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An

even parity bit will be set, if the modulo-2-sum of the seven data bits is 1. An odd parity bit will

be cleared in this case.}

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