STR720 datasheet(172/401 Pages) STMICROELECTRONICS

172 / 401 page

STR720 - UART

172/401

16.3.3

Reception

Reception is initiated by a falling edge on the data input pin (RXD), provided that the

ASCControl(Run) and ASCControl(RxEnable) bits are set. The RXD pin is sampled at 16

times the rate of the selected baud rate. A majority decision of the first, second and third

samples of the start bit determines the effective bit value. This avoids erroneous results that

may be caused by noise.

If the detected value is not a 0 when the start bit is sampled, the receive circuit is reset and

waits for the next falling edge transition at the RXD pin. If the start bit is valid, the receive

circuit continues sampling and shifts the incoming data frame into the receive shift register.

For subsequent data and parity bits, the majority decision of the seventh, eighth and ninth

samples in each bit time is used to determine the effective bit value.

Note

If reception is initiated when data input pin (RXD) is being stretched at ‘0’ a frame

error indication is reported, since reception stage samples the initial value as a falling

edge.

For 0.5 stop bits, the majority decision of the third, fourth, and fifth samples during the stop bit

is used to determine the effective stop bit value.

For 1 and 2 stop bits, the majority decision of the seventh, eighth, and ninth samples during

the stop bits is used to determine the effective stop bit values.

For 1.5 stop bits, the majority decision of the fifteenth, sixteenth, and seventeenth samples

during the stop bits is used to determine the effective stop bit value.

The effective values received on the RXD pin are shifted into a 10-bit rxshift register.

The receive fifo, rxfifo, is implemented as a 16 deep array of 10-bit vectors (each 9 down to 0).

If the rxfifo is empty, ASCstatus(RxBufNotEmpty) is set to ‘0’. If the rxfifo is not empty, a read

from ASCRx-Buffer will get the oldest entry in the rxfifo. If fifos are disabled, the rxfifo is

considered full when it contains one character. ASCStatus(RxHalfFull) is set when the rxfifo

contains more than 8 characters. Writing anything to ASCRxReset empties the rxfifo.

As soon as the effective value of the last stop bit has been determined, the content of the

rxshift register is transferred to the rxfifo (unless we’re in wake-up mode, in which case this

happens only if the wake-up bit, bit8, is a ‘1’). The receive circuit then waits for the next start

bit (falling edge transition) at the RXD pin.

ASCStatus(OverrunError) is set when the rxfifo is full and a character is loaded from the

rxshift register into the rxfifo. It is cleared when the ASCRxBuffer register is read.

The most significant bit of each rxfifo entry (rxfifo[x][9]) records whether or not there was a

frame error when that entry was received (i.e. one of the effective stop bit values was ’0’).

ASCStatus(FrameError) is set when at least one of the valid entries in the rxfifo has its MSB

set.

STR720 数据表(PDF) 172 Page - STMicroelectronics

STR720 数据表(HTML) 172 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载