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STR720 数据表(PDF) 173 Page - STMicroelectronics |
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STR720 数据表(HTML) 173 Page - STMicroelectronics |
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173 / 401 page ![]() STR720 - UART 173/401 If the mode is one where a parity bit is expected, then the bit rxfifo[x][8] (if 8 bit data + parity mode is selected) or the bit rxfifo[x][7] (if 7 bit data + parity mode is selected) records whether there was a parity error when that entry was received. Note, it does not contain the parity bit that was received. ASCStatus(ParityError) is set when at least one of the valid entries in the rxfifo has bit 8 set (if 8 bit data + parity mode is selected) or bit 7 set (if 7 bit data + parity mode is selected). After changing the fifoenable bit, it is important to reset the fifo to empty (by writing to the ASCRxReset register), since the state of the fifo pointers may be garbage. Reception is stopped by clearing the ASCControl(RxEnable) bit. A currently received frame is completed including the generation of the receive status flags. Start bits that follow this frame will not be recognized. 16.3.4 Timeout mechanism The ASC contains an 8-bit timeout counter. This reloads from ASCTimeout whenever one or more of the following is true • ASCRxBuffer is read • The ASCstarts to receive a character • ASCTimeout is written to If none of these conditions hold, the counter decrements towards 0 at every baud rate tick. ASCStatus(TimeoutNotEmpty) is ’1’ exactly whenever the rxfifo is not empty and the timeout counter is zero. ASCStatus(TimeoutIdle) is ‘1’ exactly whenever the rxfifo is empty and the timeout counter is zero. The effect of this is that whenever the rxfifo has got something in it, the timeout counter will decrement until something happens to the rxfifo. If nothing happens, and the timeout counter reaches zero, the ASCStatus(TimeoutNotEmpty) flag will be set. When the software has emptied the rxfifo, the timeout counter will reset and start decrementing. If no more characters arrive, when the counter reaches zero the ASCStatus(TimeoutIdle) flag will be set. 1 |
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