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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 180 Page - STMicroelectronics |
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STR720 数据表(HTML) 180 Page - STMicroelectronics |
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180 / 401 page  STR720 - UART 180/401 ASCControl Address Offset: 0Ch Reset value: 0000h This register controls the operating mode of the ASC and contains control bits for mode and error check selection, and status flags for error identification. Note Programming the mode control field (Mode) to one of the reserved combinations may result in unpredictable behavior. Note Serial data transmission or reception is only possible when the baud rate generator run bit (Run) is set to 1. When the Run bit is set to 0, TXD will be 1. Setting the Run bit to 0 will immediately freeze the state of the transmitter and receiver. This should only be done when the ASC is idle. Bit 15:11= Reserved. Write 0 will read back 0 Bit 10 = FifoEnable: FIFO Enable 0: FIFO mode disabled 1: FIFO mode enabled Bit 9 = Reserved. Write 0 will read back 0 Bit 8 = RxEnable: Receiver Enable 0: Receiver disabled 1: Receiver enabled Bit 7 = Run: Baudrate generator Run bit 0: Baud rate generator disabled (ASC inactive) 1: Baud rate generator enabled Bit 6 = LoopBack: LoopBack mode enable 0: Standard transmit/receive mode 1: Loopback mode enabled Note This bit may be modified only when the ASC is inactive. Bit 5 = ParityOdd: Parity selection 0: Even parity (parity bit set on odd number of ‘1’s in data) 1: Odd parity (parity bit set on even number of ‘1’s in data) 15 14 13 12 11 10 9 8 765432 1 0 RESERVED FifoEna ble RESER VED RxEnabl e Run LoopBa ck ParityO dd Stop Bits Mode rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1 |
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