STR720 datasheet(183/401 Pages) STMICROELECTRONICS

183 / 401 page

STR720 - UART

183/401

Bit 0 = ASCIntEnable[0]=RxBufNotEmptyIE: Receiver Buffer Not Empty Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

ASCStatus

Address Offset: 14h

Reset value: 0006h

The ASCStatus register determines the cause of an interrupt.

Bit 15:10 = Reserved.

Read back 0.

Bit 9 = ASCStatus[9]: TxFull.

Set when the txfifo contains 16 characters

Bit 8 = ASCStatus[8]: RxHalfFull.

Set when the rxfifo contains at least 8 characters.

Bit 7 = ASCStatus[7]: TimeoutIdle.

Set when there’s a timeout and the rxfifo is empty

Bit 6 = ASCStatus[6]: TimeoutNotEmpty.

Set when there’s a timeout and the rxfifo is not empty

Bit 5 = ASCStatus[5]: OverrunError.

Set when data is received and the rxfifo is full.

Bit 4 = ASCStatus[4]: FrameError.

Set when the rxfifo contains something received with a frame error

Bit 3 = ASCStatus[3]: ParityError.

Set when the rxfifo contains something received with a parity error

Bit 2 = ASCStatus[2]: TxHalfEmpty.

Set when txfifo at least half empty

Bit 1 = ASCStatus[1]: TxEmpty.

Set when transmit shift register is empty

Bit 0 = ASCStatus[0]: RxBufNotEmpty.

Set when rxfifo not empty (rxfifo contains at least one entry)

765432

RESERVED

ASCStatus

rrrrrr

STR720 数据表(PDF) 183 Page - STMicroelectronics

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