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STR720 数据表(PDF) 182 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 182 Page - STMicroelectronics

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STR720 - UART
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ASCIntEnable
Address Offset: 10h
Reset value 0000h
The ASCIntEnable register enables a source of interrupt.
Interrupts will occur when a status bit in the ASCStatus register is 1, and the corresponding
bit in the ASCIntEnable register is 1.
Bit 15:9 = Reserved.
Write 0, will read back 0.
Bit 8 = ASCIntEnable[8]= RxHalfFullIE: Receiver buffer Half Full Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 7 = ASCIntEnable[7]=TimeoutIdleIE: Timeout Idle Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 6 = ASCIntEnable[6]=TimeoutNotEmpty IE: Timeout Not Empty Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 5 = ASCIntEnable[5]=OverrunErrorIE: Overrun Error Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 4 = ASCIntEnable[4]=FrameErrorIE: Framing Error Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 3 = ASCIntEnable[3]=ParityErrorIE: Parity Error Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 2 = ASCIntEnable[2]=TxHalfEmptyIE: Transmitter buffer Half Empty Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
Bit 1 = ASCIntEnable[1]=TxEmptyIE: Transmitter Empty Interrupt Enable
0: interrupt disabled.
1: interrupt enabled.
15
14
13
12
11
10
9
8
765432
1
0
RESERVED
ASCIntEnable
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