STR720 datasheet(188/401 Pages) STMICROELECTRONICS

188 / 401 page

STR720 - BUFFERED SPI (BSPI)

188/401

17.3.2

BSPI Operation

During a BSPI transfer (see Figure 24 on page 188), data is shifted out and shifted in

(transmitted and received) simultaneously. The SCK line synchronizes the shifting and

sampling of the information. It is an output when the BSPI is configured as a master and an

input when the BSPI is configured as a slave. Selection of an individual slave BSPI device is

performed on the slave select line and slave devices that are not selected do not interfere with

the BSPI buses.

Figure 24. BSPI Bus Transfer

The CPOL (clock polarity) and CPHA (clock phase) bits of the BSPCSR1 are used to select

any of the four combinations of serial clock (see Figure 25 on page 189, Figure 26 on

page 189, Figure 27 on page 190 and Figure 28 on page 190). These bits must be the same

for both the master and slave BSPI devices. The clock polarity bit selects either an active high

or active low clock but does not affect transfer format. The clock phase bit selects the transfer

format.

There is a 16-bit shift register which interfaces directly to the BSPI bus lines. As transmit data

goes out from the register, received data fills the register.

Note

When BSPI cell is configured in Slave mode, SCLK_IN clock must be divided by a

factor of 8 or more compared with the configured peripheral clock (APB clock).

In case a clock polarity change is required when BSPI macrocell is configured in master

mode, the following sequence should be followed in order to avoid spurious clock edges

generation:

1. Write ‘0’ into both MSTR and BSPE bit in BSPCSR1 register, so to safely disable BSPI

macrocell.

2. Change CPOL and CPHA bits in BSPCSR1 register according to the required polarity set-

ting.

3. Write ‘1’ into BSPE bit of BSPCSR1 register to enable again BSPI macrocell.

4. Write ‘1’ into MSTR bit of BSPCSR1 register to configure the master mode again.

It must be noticed that the above sequence should be executed as reported, without merging

in a single instruction any of the steps.

MOSI/MISO

SCK

DATA1

8 bits

DATA0

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