STR720 datasheet(192/401 Pages) STMICROELECTRONICS

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STR720 - BUFFERED SPI (BSPI)

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17.3.5

Start-up Status

If the BSPI is to operate in Master mode, it must first be enabled, then the MSTR bit must be

set high. The TFE flag will be set, signalling that the Transmit FIFO is empty, if the TIE is set,

a TFE interrupt will be generated. The data to be transferred must be written to the Transmit

Data Register, the TFE interrupt will be cleared and then the BSPI clock will be generated

according to the value of the BSPCLK register. The Transfer of data then begins. A second

TFE interrupt occurs so that the peripheral has a full data transfer time to request the data

before the next transfer is to begin.

If the BSPI is to operate in slave mode, once again the device must be enabled. The SS line

must only be asserted low after the SCK from the master is stable. The TFE flag will be set,

depending on the BSPI being enabled, signalling that the Transmit Data register is empty and

will be cleared by a write to the Transmit Data register. The second TFE interrupt occurs to

request data for the following transfer.

17.3.6

Clocking problems and clearing of the shift-register

Should a problem arise on the clock which results in a misalignment of data in the shift

setting the TFE which requests data to be written to the Transmit Register for the next transfer.

Clearing the BSPI enable will also reset the counter of bits received. The next block of data

received will be written to the next location in the FIFO continuing on from the last good

transfer. If the FIFO was just one word deep it will be written to the only location available.

17.3.7

Interrupt control

The BSPI generates one interrupt based upon the status bits monitoring the transmit and

receive logic. The interrupt is acknowledged or cleared by subsequent read or write

operations which remove the error or status update condition. It is the responsibility of the

programmer to ascertain the source of the interrupt and then remove the error condition or

alter the state of the BSPI. In the case of multiple errors the interrupt will remain active until all

interrupt sources have been cleared.

For example, in the case of TFE, whenever the last word has been transferred to the transmit

buffer, the TFE flag is asserted. If interrupts are enabled then an interrupt will be asserted to

the processor. To clear the interrupt the user must write at least one data word into the FIFO,

or disable the interrupts if this condition is valid.

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