STR720 datasheet(195/401 Pages) STMICROELECTRONICS

195 / 401 page

STR720 - BUFFERED SPI (BSPI)

195/401

Bit 9 = CPHA: Clock Phase Select.

Used with the CPOL bit to define the master-slave clock relationship. When CPHA=0, as soon

as the SS goes low the first data sample is captured on the first edge of SCK. When CPHA=1,

the data is captured on the second edge.

Bit 8 = CPOL: Clock Polarity Select.

When this bit is cleared and data is not being transferred, a stable low value is present on the

SCK pin. If the bit is set the SCK pin will idle high. This bit is used with the CPHA bit to define

the master-slave clock relationship.

0 = Active high clocks selected; SCK idles low.

1 = Active low clocks selected; SCK idles high.

Bit 7 = BEIE: Bus Error Interrupt Enable.

When this bit is set to ‘1’, an interrupt will be asserted to the processor whenever a Bus Error

condition occurs.

Bit 6 = Reserved.

To be left at 0 level (reset status).

Bit 5 = Reserved.

To be left at 0 level (reset status).

Bit 4 = REIE: Receive Error Interrupt Enable.

When this bit is set to ‘1’ and the Receiver Overflow error condition occurs, a Receive Error

Interrupt will be asserted to the processor.

Bits 3:2 = RIE[1:0]: BSPI Receive Interrupt Enables.

The RIE1:0 bits are interrupt enables which configure when the processor will be interrupted

on received data. The following configurations are possible.

Bit 1 = MSTR: Master/Slave Select.

1: BSPI is configured as a master

0: BSPI is configured as a slave

Bit 0 = BSPE: BSPI System Enable.

1: BSPI system is enabled

0: BSPI system is disabled

Note

The peripheral should be enabled before selecting the interrupts. In this way the

application software can avoid unexpected behaviours of interrupt request signal.

RIE1

RIE0

Interrupted on

Disabled

Receive FIFO Not Empty

Reserved

Receive FIFO Full

STR720 数据表(PDF) 195 Page - STMicroelectronics

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