STR720 datasheet(196/401 Pages) STMICROELECTRONICS

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STR720 - BUFFERED SPI (BSPI)

196/401

BSPI Control/Status Register 2 (BSPCSR2)

Address Offset: 0Ch

Reset value: 0040h

Bits 15:14 = TIE[1:0]: BSPI Transmit Interrupt Enable.

These bits control the source of the transmit interrupt.

Bits 13:10 = TFE[3:0]: Transmit FIFO Enable.

These bits control the depth of the transmit FIFO. The table below indicates all valid settings.

Bit 9 = TFNE: Transmit FIFO Not Empty.

This bit is set whenever the FIFO contains at least one data word.

Bit 8 = TFF: Transmit FIFO Full.

TFF is set whenever the number of words written to the transmit FIFO is equal to the number

765432

TIE[1:0]

TFE[3:0]

TFNE

TFF

TUFL

TFE

ROFL

RFF

RFNE

BERR

Res.

DFIFO

rrrrr

TIE1

TIE0

Interrupted on

Disabled

Transmit FIFO Empty

Transmit underflow (only in Master mode)

Transmit FIFO Full

TFE[3:0]

Depth of FIFO

0000

1st word enabled

0001

1st & 2nd words enabled

0010

1-3 words enabled

0011

1-4 words enabled

0100

1-5 words enabled

0101

1-6 words enabled

0110

1-7 words enabled

0111

1-8 words enabled

1000

1-9 words enabled

1001

1-10 words enabled

1010

1-11words enabled

1011

1-12words enabled

1100

1-13words enabled

1101

1-14words enabled

1110

1-15words enabled

1111

1-16words enabled

STR720 数据表(PDF) 196 Page - STMicroelectronics

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