STR720 datasheet(200/401 Pages) STMICROELECTRONICS

200 / 401 page

STR720 - BUFFERED SPI (BSPI)

200/401

BSPI Master Clock Divider Register (BSPCLK)

Address Offset: 10h

Reset value: 0006h

Bits 15:8 = Reserved.

To be left at 0 level (reset status).

Bits 7:0 = DIV[7:0]: Divide factor bits.

These bits are used to control the frequency of the BSPI serial clock with relation to the device

clock APB_CLK. In master mode this number must be an even number greater than five, i.e.

six is the lowest divide factor. In slave mode this number must be an even number greater

than seven, i.e. eight is the lowest divide factor.

These bits must be set before the BSPE or MSTR bits, i.e. before the BSPI is configured into

master mode.

BSPI Transmit Register (BSPTXR)

Address Offset: 04h

Reset value: n/a

Bits 15:0 = TX[15:0]: Transmit data.

This register is used to write data for transmission into the BSPI. If the FIFO is enabled then

data written to this register will be transferred to the FIFO before transmission. If the FIFO is

disabled then the register contents are transferred directly to the shift register for

transmission. In sixteen bit mode all of the register bits are used. In eight bit mode only the

upper eight bits of the register are used while lower eight bits are ignored. In both case the

data is left justified, i.e. Bit[15] = MSB, Bit[0] / Bit[8] = LSB depending on the operating mode.

765432

reserved

DIV[7:0]

-rw

16 bit Transmission

TX[15:0]

8 bit Transmission

TX[7:0]

Not Used

STR720 数据表(PDF) 200 Page - STMicroelectronics