STR720 datasheet(198/401 Pages) STMICROELECTRONICS

198 / 401 page

STR720 - BUFFERED SPI (BSPI)

198/401

Bit 1 = Reserved.

To be left at 0 level (reset status).

Bit 0 = DFIFO: Disable for the FIFO.

When this bit is enabled, the FIFO pointers are all reset to zero, the RFE bits are set to zero

and therefore the BSPI is set to one location. The data within the FIFO is lost. This bit is reset

to zero after a clock cycle.

BSPI Control/Status Register 3 (BSPCSR3)

Address Offset: 14h

Reset value: 0000h

This register is used to control the BSPI DMA interface. When the BSPI is receiving da-

ta, it will be the source of DMA transfer and system memory will act as destination.

Conversely, when the BSPI is in transmit mode, it is sending data to an external source

and it will act as DMA destination while system memory will be the source.

Bits 15:8 = Reserved. These bits must be always written to ‘0’.

Bit 7 = RREQ_EN: Receive REQuest ENable

This is the enable bit for the reception DMA request and it flags the DMA controller that an

amount of data corresponding at least to the configured reception burst length is available in

the BSPI receive FIFO to be transferred.

0 = Receive DMA requests are disabled.

1 = Receive DMA requests are enabled.

Bit 6 = TREQ_EN: Transmit REQuest ENable

This is the enable bit for the transmission DMA request and it flags the DMA controller that in

the BSPI transmit FIFO there is an amount of free locations corresponding at least to the

configured transmission burst length.

0 = Transmit DMA requests are disabled.

1 = Transmit DMA requests are enabled.

Bits 5:4 = RBURST_LEN[1:0]: Receive BURST LENgth

These bits configure the burst length when the BSPI receives data. This programmable length

is used to set the number of data words the DMA controller is expected to retrieve upon a

receive request; this value is used in the DMA interface to determine when the BSPI is ready

to send a data burst to the DMA. A word can be 16 bit or 8 bit wide according to the

configuration set in WL bits inside BSPCSR1 register.

765432

Reserved

RREQ

_EN

TREQ

_EN

RBURST_LEN

[1:0]

TBURST_LEN

[1:0]

DMA

_EN

MASK

_SS

-rw

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