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STR720 数据表(PDF) 201 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 201 Page - STMicroelectronics

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STR720 - BUFFERED SPI (BSPI)
201/401
BSPI Receive Register (BSPRXR)
Address Offset: 00h
Reset value: 0000h
Bits 15:0 = RX[15:0]: Received data.
This register contains the data received from the BSPI bus. If the FIFO is disabled then the
data from the shift register is placed into the receive register directly. If the FIFO is enabled
then the received data is transferred into the FIFO. In sixteen bit mode all the register bits are
utilized. In eight bit reception mode the received data is replicated on the upper and lower
eight bits of the register so to support both little and big endian memory systems.
17.4.1
Register map
A summary overview of the BSPI registers is given in the following table.
(*)Data is justified depending on transmission mode, Bit 15 = MSB.
Refer to Table 20 on page 49 for the base address.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16 bit Reception
RX[15:0]
8 bit Reception
RX[7:0]
RX[7:0]
r
Table 47. BSPI Register Map
Addr.
Offset
Register
Name
15
14
13
12
11
10
9876543210
0
BSPRXR
RX[15:0] (*)
04
BSPTXR
TX[15:0] (*)
08
BSPCSR1
RFE[3:0]
WL[1:0]
CPHA
CPOL
BEIE
Reserved
REIE
RIE[1:0]
MSTR
BSPE
0C
BSPCSR2
TIE[1:0]
TFE[3:0]
TFNE
TFF
TUFL
TFE
ROFL
RFF
RFNE
BERR
Res.
DFIFO
10
BSPCLK
Reserved
DIV[7:0]
14
BSPCSR3
Reserved
RREQ
_EN
TREQ_
EN
RBURST_
LEN[1:0]
TBURST_
LEN [1:0]
DMA
_EN
MASK
_SS
1



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