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STR720 数据表(PDF) 193 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 193 Page - STMicroelectronics

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STR720 - BUFFERED SPI (BSPI)
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17.3.8
DMA Interface
The DMA interface is a feature of the BSPI that allows data to be transferred to or from system
memory using a DMA controller instead of main CPU. Data can be transferred in single data
accesses or in burst mode, the amount of words being selectable by the programmer, thus
making efficient more use of system bus. The BSPI DMA interface has the following features:
1) The DMA interface can be totally disabled using a bit in BSPCSR3 register.
2) User programmable burst size: 1, 4, 8 or 16 words can be transferred at a time.
3) Two request lines to the DMA are generated: one dedicated to the BSPI operating in
transmit mode and another dedicated to the BSPI operating in receive mode. These signals
are generated in independently from each other inside the BSPI.
4) Received 8-bit data, being sent from the BSPI to the memory, is arranged in a format which
is compatible both with little and big endian convention, replicating the received data on both
high and low byte in BSPRXR register.
The DMA interface makes use of pointers inside both the transmit and receive fifo (these
being independent of one another) in order for it to decide when a DMA request to transmit or
receive data can be made. The choice of burst size should match the one configured in the
corresponding DMA channel.
Note
There is a restriction on the burst capability of DMA interface during reception. The
total number of words to be transferred to system memory via DMA must be an
integer multiple of the programmed Burst Length size, since DMA interface is not
capable of handling incomplete received burst transfers. For example if Burst Length
size is set to 4 and at the end of received data transfer BSPI FIFO has only 3 spaces,
no request would be issued. On the contrary, with an even divide, the last chunk of
received data will always be equal to the programmed size of the burst length.
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