STR720 datasheet(191/401 Pages) STMICROELECTRONICS

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STR720 - BUFFERED SPI (BSPI)

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17.3.3

Transmit FIFO

The transmit FIFO consists of a 16 by 16 bit register bank which can operate in 8/16 bit modes

as configured by the word length (WL[1:0]) control bits of BSPCSR1. Data is left justified

indicating that only the most significant portion of the word is transmitted if using 8 bit mode.

After a transmission is completed the next data word is loaded from the transmit FIFO.

The user can set the depth of the FIFO from the default one location up to a maximum of

sixteen locations. This can be set dynamically but will only take effect after the completion of

the current transmission. Status flags report if the FIFO is full (TFF), the FIFO is not empty

(TFNE), the FIFO is empty (TFE) and the transmit buffer has under flown (TUFL), this last one

being generated only when macrocell is configured in master mode. The transmit interrupt

enable (TIE[1:0]) control bits of BSPCSR2 determine the source of the transmit interrupt. If

the interrupt source is enabled then an active high interrupt will be asserted to the processor.

If BSPI is configured in master mode and the TUFL flag is asserted then a subsequent write

to the transmit FIFO will clear the flag. If interrupts are enabled the interrupt will be

de-asserted. Regardless of the selected BSPI mode, TFF and TFNE flags are updated at the

end of the processor write cycle and at the end of each transmission.

Note

Data should be written in the fifo only if the macro is enabled (see BSPI System

Enable bit of BSPI Control Register). If one data word is written in the trasmit fifo

before enabling the BSPI no data will be transmitted.

Note

When it is necessary to be notified about the end of last word transmission, TUFL

event can be used for the purpose, provided BSPI is configured in master mode. In

case this notification is required also when BSPI is configured as a slave, the end of

transmission cannot be detected and a suitable wait loop must be implemented.

17.3.4

Receive FIFO

The BSPI Receive FIFO is a 16 word by 16-bit FIFO used to buffer the data words received

from the BSPI bus.

The FIFO can operate in 8-bit and 16-bit modes as configured by the WL[1:0] bits of the

BSPCSR1 register. Irrelevant of the word depth in the FIFO, if operating in 8-bit mode, the

data will occupy both the Most Significant and the Least Significant Bytes of each location of

the FIFO (data can be used either as left or right justified).

The receive FIFO enable bits RFE[3:0] declare how many words deep the FIFO is for all

transfers. The FIFO defaults to one word deep. Whenever there is at least one block of data in

the FIFO the RFNE bit is set in the BSPCSR2 register, i.e there is data in at least one location.

The RFF flag does not get set until all locations of the FIFO contain data, i.e. RFF is set when

the depth of FIFO is filled and nothing has been read out.

If the FIFO is one word deep then the RFNE and RFF flags are set once data is written to it.

When the data is read then both flags are cleared. A write to and a read from the FIFO can

happen independent of each once RFF is not set, if RFF is set a read must occur before the

next write or an overflow (ROFL) will occur.

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