STR720 datasheet(248/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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18.7.9

Handling Interrupts

If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt

with the highest priority, disregarding their chronological order. An interrupt remains pending

until the application software has cleared it.

The Status Interrupt has the highest priority. Among the message interrupts, interrupt priority

of the Message Object decreases with increasing message number.

A message interrupt is cleared by clearing the IntPnd bit of the Message Object. The Status

Interrupt is cleared by reading the Status Register.

The interrupt identifier, IntId, in the Interrupt Register, indicates the cause of the interrupt.

When no interrupt is pending, the register will hold the value zero. If the value of the Interrupt

interrupt signal to the EIC is active. The interrupt remains active until the Interrupt Register is

back to value zero (the cause of the interrupt is reset) or until IE is reset.

The value 0x8000 indicates that an interrupt is pending because the CAN Core has updated

(not necessarily changed) the Status Register (Error Interrupt or Status Interrupt). This

interrupt has the highest priority. The CPU can update (reset) the status bits RxOk, TxOk and

LEC, but a write access of the CPU to the Status Register can never generate or reset an

interrupt.

All other values indicate that the source of the interrupt is one of the Message Objects. IntId

points to the pending message interrupt with the highest interrupt priority.

The CPU controls whether a change of the Status Register may cause an interrupt (bits EIE

and SIE in the CAN Control Register) and whether the interrupt line becomes active when the

Interrupt Register is different from zero (bit IE in the CAN Control Register). The Interrupt

The CPU has two possibilities to follow the source of a message interrupt. First, it can follow

the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register (see

See “Interrupt Pending Registers 1 & 2 (CAN_IPnR)” on page 235.).

An interrupt service routine that is reading the message that is the source of the interrupt may

read the message and reset the Message Object’s IntPnd at the same time (bit ClrIntPnd in

the Command Mask Register). When IntPnd is cleared, the Interrupt Register will point to the

next Message Object with a pending interrupt.

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