STR720 datasheet(251/401 Pages) STMICROELECTRONICS

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STR720 - CONTROLLER AREA NETWORK (CAN)

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18.7.10.2 Propagation Time Segment

This part of the bit time is used to compensate physical delay times within the network. These

delay times consist of the signal propagation time on the bus and the internal delay time of the

CAN nodes.

Any CAN node synchronized to the bit stream on the CAN bus will be out of phase with the

transmitter of that bit stream, caused by the signal propagation time between the two nodes.

The CAN protocol’s non-destructive bitwise arbitration and the dominant acknowledge bit

provided by receivers of CAN messages requires that a CAN node transmitting a bit stream

must also be able to receive dominant bits transmitted by other CAN nodes that are

synchronized to that bit stream. The example in Figure 36 shows the phase shift and

propagation times between two CAN nodes.

In this example, both nodes A and B are transmitters, performing an arbitration for the CAN

bus. Node A has sent its Start of Frame bit less than one bit time earlier than node B, therefore

node B has synchronized itself to the received edge from recessive to dominant. Since node

B has received this edge delay (A_to_B) after it has been transmitted, B’s bit timing segments

are shifted with respect to A. Node B sends an identifier with higher priority and so it will win

the arbitration at a specific identifier bit when it transmits a dominant bit while node A

transmits a recessive bit. The dominant bit transmitted by node B will arrive at node A after the

delay (B_to_A).

Due to oscillator tolerances, the actual position of node A’s Sample Point can be anywhere

inside the nominal range of node A’s Phase Buffer Segments, so the bit transmitted by node B

Figure 36. Propagation Time Segment

Sync_Seg

Prop_Seg

Phase_Seg1

Phase_Seg2

Node B

Node A

Delay A_to_B

Delay B_to_A

Prop_Seg

>= Delay A_to_B + Delay B_to_A

Prop_Seg

>= 2 • [max(node output delay+ bus line delay + node input delay)]

Delay A_to_B >= node output delay(A) + bus line delay(A

→B) + node input delay(B)

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