STR720 datasheet(252/401 Pages) STMICROELECTRONICS

252 / 401 page

STR720 - CONTROLLER AREA NETWORK (CAN)

252/401

must arrive at node A before the start of Phase_Seg1. This condition defines the length of

Prop_Seg.

If the edge from recessive to dominant transmitted by node B arrives at node A after the start

of Phase_Seg1, it can happen that node A samples a recessive bit instead of a dominant bit,

resulting in a bit error and the destruction of the current frame by an error flag.

The error occurs only when two nodes arbitrate for the CAN bus that have oscillators of

opposite ends of the tolerance range and that are separated by a long bus line. This is an

example of a minor error in the bit timing configuration (Prop_Seg to short) that causes

sporadic bus errors.

Some CAN implementations provide an optional 3 Sample Mode but the CAN Peripheral does

not. In this mode, the CAN bus input signal passes a digital low-pass filter, using three

samples and a majority logic to determine the valid bit value. This results in an additional input

delay of 1 tq, requiring a longer Prop_Seg.

18.7.10.3 Phase Buffer Segments and Synchronization

The Phase Buffer Segments (Phase_Seg1 and Phase_Seg2) and the Synchronization Jump

Width (SJW) are used to compensate for the oscillator tolerance. The Phase Buffer Segments

may be lengthened or shortened by synchronization.

Synchronizations occur on edges from recessive to dominant, their purpose is to control the

distance between edges and Sample Points.

Edges are detected by sampling the actual bus level in each time quantum and comparing it

with the bus level at the previous Sample Point. A synchronization may be done only if a

recessive bit was sampled at the previous Sample Point and if the bus level at the actual time

quantum is dominant.

An edge is synchronous if it occurs inside of Sync_Seg, otherwise the distance between edge

and the end of Sync_Seg is the edge phase error, measured in time quanta. If the edge

occurs before Sync_Seg, the phase error is negative, else it is positive.

Two types of synchronization exist, Hard Synchronization and Re-synchronization.

A Hard Synchronization is done once at the start of a frame and inside a frame only when

Re-synchronizations occur.

•

Hard Synchronization

After a hard synchronization, the bit time is restarted with the end of Sync_Seg,

regardless of the edge phase error. Thus hard synchronization forces the edge, which has

caused the hard synchronization to lie within the synchronization segment of the restarted

bit time.

•

Bit Re-synchronization

Re-synchronization leads to a shortening or lengthening of the bit time such that the

position of the sample point is shifted with regard to the edge.

STR720 数据表(PDF) 252 Page - STMicroelectronics

STR720 数据表(HTML) 252 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载