STR720 datasheet(267/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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scheme implements a virtual dual-port RAM that allows memory access, while an USB

transaction is happening. Multi-word APB transfers of any length are also allowed by this

scheme.

•

USB Peripheral in a structured 16-bit wide word set addressed by the APB.

•

Interrupt Mapper: This block is used to select how the possible USB events can generate

interrupts and map them to IRQ lines of the EIC.

•

APB Wrapper: This provides an interface to the APB for the memory and register. It also

maps the whole USB Peripheral in the APB address space.

19.5 Programming Considerations

In the following sections, the expected interactions between the USB Peripheral and the

application program are described, in order to ease application software development.

19.5.1

Generic USB Device Programming

This part describes the main tasks required of the application software in order to obtain USB

compliant behaviour. The actions related to the most general USB events are taken into

account and paragraphs are dedicated to the special cases of double-buffered endpoints and

Isochronous transfers. Apart from system reset, action is always initiated by the USB

Peripheral, driven by one of the USB events described below.

19.5.2

System and Power-On Reset

Upon system and power-on reset, the first operation the application software should perform

is to provide all required clock signals to the USB Peripheral and subsequently de-assert its

reset signal so to be able to access its registers. The whole initialization sequence is hereafter

described.

As a first step application software needs to activate register macrocell clock and de-assert

macrocell specific reset signal using related control bits provided by device clock

management logic.

After that the analog part of the device related to the USB transceiver must be switched on

using the PDWN bit in CNTR register which requires a special handling. This bit is intended to

switch on the internal voltage references supplying the port transceiver . Since this circuits

have a defined start-up time, during which the behaviour of USB transceiver is not defined, it

is necessary to wait this time, after having set the PDWN bit in CNTR register, then the reset

condition on the USB part can be removed (clearing of FRES bit in CNTR register) and the

ISTR register can be cleared, removing any spurious pending interrupt, before enabling any

other macrocell operation.

As a last step the USB specific 48 MHz clock needs to be activated, using the related control

bits provided by device clock management logic, where applicable.

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