STR720 datasheet(268/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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At system reset, the microcontroller must initialize all required registers and the packet buffer

description table, to make the USB Peripheral able to properly generate interrupts and data

transfers. All registers not specific to any endpoint must be initialized according to the needs

of application software (choice of enabled interrupts, chosen address of packet buffers, etc.).

Then the process continues as for the USB reset case (see further paragraph).

19.5.2.1 USB Reset (RESET Interrupt)

When this event occurs, the USB Peripheral is put in the same conditions it is left by the

system reset after the initialization described in the previous paragraph: the USB_DADDR

will not respond to any packet). As a response to the USB reset event, the USB function must

be enabled, having as USB address 0, implementing only the default control endpoint

(endpoint address is 0 too). This is accomplished by setting the Enable Function (EF) bit of

the USB_DADDR register and initializing the EP0R register and its related packet buffers

accordingly. During USB enumeration process, the host assigns a unique address to this

device, which must be written in the ADD[6:0] bits of the USB_DADDR register, and

configures any other necessary endpoint.

When a RESET interrupt is received, the application software is responsible to enable again

the default endpoint of USB function 0 within 10mS from the end of reset sequence which

triggered the interrupt.

19.5.2.2 Structure and Usage of Packet Buffers

Each bidirectional endpoint may receive or transmit data from/to the host. The received data

is stored in a dedicated memory buffer reserved for that endpoint, while another memory

buffer contains the data to be transmitted by the endpoint. Access to this memory is

performed by the packet buffer interface block, which delivers a memory access request and

waits for its acknowledgement. Since the packet buffer memory has to be accessed by the

microcontroller also, an arbitration logic takes care of the access conflicts, using half APB

cycle for microcontroller access and the remaining half for the USB Peripheral access. In this

way, both the agents can operate as if the packet memory is a dual-port RAM, without being

aware of any conflict even when the microcontroller is performing back-to-back accesses. The

USB Peripheral logic uses a dedicated clock. The frequency of this dedicated clock is fixed by

the requirements of the USB standard at 48 MHz, and this can be different from the clock

used for the interface to the APB bus. Different clock configurations are possible where the

APB clock frequency can be higher or lower than the USB Peripheral one. However, due to

USB data rate and packet memory interface requirements, the APB clock frequency must be

greater than 8 MHz to avoid data overrun/underrun problems.

Each endpoint is associated with two packet buffers (usually one for transmission and the

other one for reception). The size of the buffer can be upto 512 words each. Buffers can be

placed anywhere inside the packet memory because their location and size is specified in a

buffer description table, which is also located in the packet memory at the address indicated

by the USB_BTABLE register. Each table entry is associated to an endpoint register and it is

composed of four 16-bit words so that table start address must always be aligned to an 8-byte

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