STR720 datasheet(272/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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When the transaction is completed correctly, by sending the ACK handshake packet, the

internal COUNT register is copied back in the COUNTn_RX location inside the buffer

description table entry, leaving unaffected BL_SIZE and NUM_BLOCK fields, which normally

do not require to be re-written, and the USB_EPnR register is updated in the following way:

DTOG_RX bit is toggled, the endpoint is made invalid by setting STAT_RX = ‘10’ (NAK) and bit

CTR_RX is set. If the transaction has failed due to errors or buffer overrun condition, none of

the previously listed actions take place. The application software must first identify the

endpoint, which is requesting microcontroller attention by examining the EP_ID and DIR bits

in the USB_ISTR register. The CTR_RX event is serviced by first determining the transaction

type (SETUP bit in the USB_EPnR register); the application software must clear the interrupt

flag bit and get the number of received bytes reading the COUNTn_RX location inside the

buffer description table entry related to the endpoint being processed. After the received data

is processed, the application software should set the STAT_RX bits to ‘11’ (Valid) in the

USB_EPnR, enabling further transactions. While the STAT_RX bits are equal to ‘10’ (NAK),

any OUT request addressed to that endpoint is NAKed, indicating a flow control condition: the

USB host will retry the transaction until it succeeds. It is mandatory to execute the sequence

of operations in the above mentioned order to avoid losing the notification of a second OUT

transaction addressed to the same endpoint following immediately the one which triggered

the CTR interrupt.

19.5.2.6 Control Transfers

Control transfers are made of a SETUP transaction, followed by zero or more data stages, all

of the same direction, followed by a status stage (a zero-byte transfer in the opposite

direction). SETUP transactions are handled by control endpoints only and are very similar to

OUT ones (data reception) except that the values of DTOG_TX and DTOG_RX bits of the

addressed endpoint registers are set to 1 and 0 respectively, to initialize the control transfer,

and both STAT_TX and STAT_RX are set to ‘10’ (NAK) to let software decide if subsequent

transactions must be IN or OUT depending on the SETUP contents. A control endpoint must

check SETUP bit in the USB_EPnR register at each CTR_RX event to distinguish normal

OUT transactions from SETUP ones. A USB device can determine the number and direction

of data stages by interpreting the data transferred in the SETUP stage, and is required to

STALL the transaction in the case of errors. To do so, at all data stages before the last, the

unused direction should be set to STALL, so that, if the host reverses the transfer direction too

soon, it gets a STALL as a status stage. While enabling the last data stage, the opposite

direction should be set to NAK, so that, if the host reverses the transfer direction (to perform

the status stage) immediately, it is kept waiting for the completion of the control operation. If

the control operation completes successfully, the software will change NAK to VALID,

otherwise to STALL. At the same time, if the status stage will be an OUT, the STATUS_OUT

(EP_KIND in the USB_EPnR register) bit should be set, so that an error is generated if a

status transaction is performed with not-zero data. When the status transaction is serviced,

the application clears the STATUS_OUT bit and sets STAT_RX to VALID (to accept a new

command) and STAT_TX to NAK (to delay a possible status stage immediately following the

next setup).

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