STR720 datasheet(276/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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19.5.4

Isochronous Transfers

The USB standard supports full speed peripherals requiring a fixed and accurate data

production/consume frequency, defining this kind of traffic as ‘Isochronous’. Typical examples

of this data are: audio samples, compressed video streams, and in general any sort of

sampled data having strict requirements for the accuracy of delivered frequency. When an

endpoint is defined to be ‘isochronous’ during the enumeration phase, the host allocates in

the frame the required bandwidth and delivers exactly one IN or OUT packet each frame,

depending on endpoint direction. To limit the bandwidth requirements, no re-transmission of

failed transactions is possible for Isochronous traffic; this leads to the fact that an isochronous

transaction does not have a handshake phase and no ACK packet is expected or sent after

the data packet. For the same reason, Isochronous transfers do not support data toggle

sequencing and always use DATA0 PID to start any data packet.

The Isochronous behaviour for an endpoint is selected by setting the EP_TYPE bits at ‘10’ in

its USB_EPnR register; since there is no handshake phase the only legal values for the

STAT_RX/STAT_TX bit pairs are ‘00’ (Disabled) and ‘11’ (Valid), any other value will produce

results not compliant to USB standard. Isochronous endpoints implement double-buffering to

ease application software development, using both ‘transmission’ and ‘reception’ packet

memory areas to manage buffer swapping on each successful transaction in order to have

always a complete buffer to be used by the application, while the USB Peripheral fills the

other.

The memory buffer which is currently used by the USB Peripheral is defined by the DTOG bit

related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints, DTOG_TX

for ‘transmission’ isochronous endpoints, both in the related USB_EPnR register) according

to Table 60.

As it happens with double-buffered bulk endpoints, the USB_EPnR registers used to

implement Isochronous endpoints are forced to be used as uni-directional ones. In case it is

required to have Isochronous endpoints enabled both for reception and transmission, two

USB_EPnR registers must be used.

The application software is responsible for the DTOG bit initialization according to the first

buffer to be used; this has to be done considering the special toggle-only property that these

Table 60. Isochronous Memory Buffers Usage

DTOG bit value

DMA buffer used by

USB Peripheral

DMA buffer used by

application software

ADDRn_TX / COUNTn_TX

buffer description table

locations.

ADDRn_RX / COUNTn_RX

buffer description table

locations.

ADDRn_RX / COUNTn_RX

buffer description table

locations.

ADDRn_TX / COUNTn_TX

buffer description table

locations.

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