STR720 datasheet(277/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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two bits have. At the end of each transaction, the CTR_RX or CTR_TX bit of the addressed

endpoint USB_EPnR register is set, depending on the enabled direction. At the same time,

the affected DTOG bit in the USB_EPnR register is hardware toggled making buffer swapping

completely software independent. STAT bit pair is not affected by transaction completion;

since no flow control is possible for Isochronous transfers due to the lack of handshake phase,

the endpoint remains always ‘11’ (Valid). CRC errors or buffer-overrun conditions occurring

during Isochronous OUT transfers are anyway considered as correct transactions and they

always trigger an CTR_RX event. However, CRC errors will anyway set the ERR bit in the

USB_ISTR register to notify the software of the possible data corruption.

19.5.5

Suspend/Resume Events

The USB standard defines a special peripheral state, called SUSPEND, in which the average

current drawn from the USB bus must not be greater than 500

µA. This requirement is of

fundamental importance for bus-powered devices, while self-powered devices are not

required to comply to this strict power consumption constraint. In suspend mode, the host PC

sends the notification to not send any traffic on the USB bus for more than 3mS: since a SOF

packet must be sent every mS during normal operations, the USB Peripheral detects the lack

of 3 consecutive SOF packets as a suspend request from the host PC and set the SUSP bit to

‘1’ in USB_ISTR register, causing an interrupt if enabled. Once the device is suspended, its

normal operation can be restored by a so called RESUME sequence, which can be started

from the host PC or directly from the peripheral itself, but it is always terminated by the host

PC. The suspended USB Peripheral must be anyway able to detect a RESET sequence,

reacting to this event as a normal USB reset event.

The actual procedure used to suspend the USB peripheral is device dependent since

according to the device composition, different actions may be required to reduce the total

consumption.

A brief description of a typical suspend procedure is provided below, focused on the USB-

related aspects of the application software routine responding to the SUSP notification of the

USB Peripheral:

1. Set the FSUSP bit in the USB_CNTR register to 1. This action activates the suspend

mode within the USB Peripheral. As soon as the suspend mode is activated, the check on

SOF reception is disabled to avoid any further SUSP interrupts being issued while the

USB is suspended.

2. Remove or reduce any static power consumption in blocks different from the USB Periph-

eral.

3. Set LP_MODE bit in USB_CNTR register to 1 to remove static power consumption in the

analog USB transceivers but keeping them able to detect resume activity.

4. Optionally turn off external oscillator and device PLL to stop any activity inside the device.

When an USB event occurs while the device is in SUSPEND mode, the RESUME procedure

must be invoked to restore nominal clocks and regain normal USB behaviour. Particular care

must be taken to insure that this process does not take more than 10mS when the wakening

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