STR720 datasheet(271/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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requesting microcontroller attention by examining the EP_ID and DIR bits in the USB_ISTR

software then prepares another buffer full of data to be sent, updates the COUNTn_TX table

location with the number of byte to be transmitted during the next transfer, and finally sets

STAT_TX to ‘11’ (VALID) to re-enable transmissions. While the STAT_TX bits are equal to ‘10’

(NAK), any IN request addressed to that endpoint is NAKed, indicating a flow control

condition: the USB host will retry the transaction until it succeeds. It is mandatory to execute

the sequence of operations in the above mentioned order to avoid losing the notification of a

second IN transaction addressed to the same endpoint immediately following the one which

triggered the CTR interrupt.

19.5.2.5 OUT and SETUP Packets (Data Reception)

These two tokens are handled by the USB Peripheral more or less in the same way; the

differences in the handling of SETUP packets are detailed in the following paragraph about

control transfers. When receiving an OUT/SETUP PID, if the address matches a valid

endpoint, the USB Peripheral accesses the contents of the ADDRn_RX and COUNTn_RX

locations inside the buffer descriptor table entry related to the addressed endpoint. The

content of the ADDRn_RX is stored directly in its internal register ADDR. While COUNT is

now reset and the values of BL_SIZE and NUM_BLOCK bit fields, which are read within

COUNTn_RX content are used to initialize BUF_COUNT, an internal 16 bit counter, which is

used to check the buffer overrun condition (all these internal registers are not accessible by

software). Data bytes subsequently received by the USB Peripheral are packed in words (the

first byte received is stored as least significant byte) and then transferred to the packet buffer

starting from the address contained in the internal ADDR register while BUF_COUNT is

decremented and COUNT is incremented at each byte transfer. When the end of DATA packet

is detected, the correctness of the received CRC is tested and only if no errors occurred

during the reception, an ACK handshake packet is sent back to the transmitting host. In case

of wrong CRC or other kinds of errors (bit-stuff violations, frame errors, etc.), data bytes are

anyways copied in the packet memory buffer, at least until the error detection point, but ACK

packet is not sent and the ERR bit in USB_ISTR register is set. However, there is usually no

software action required in this case: the USB Peripheral recovers from reception errors and

remains ready for the next transaction to come. If the addressed endpoint is not valid, a NAK

or STALL handshake packet is sent instead of the ACK, according to bits STAT_RX in the

USB_EPnR register and no data is written in the reception memory buffers.

Reception memory buffer locations are written starting from the address contained in the

ADDRn_RX for a number of bytes corresponding to the received data packet length, CRC

included (i.e. data payload length + 2), or up to the last allocated memory location, as defined

by BL_SIZE and NUM_BLOCK, whichever comes first. In this way, the USB Peripheral never

writes beyond the end of the allocated reception memory buffer area. If the length of the data

packet payload (actual number of bytes used by the application) is greater than the allocated

buffer, the USB Peripheral detects a buffer overrun condition. in this case, a STALL

handshake is sent instead of the usual ACK to notify the problem to the host, no interrupt is

generated and the transaction is considered failed.

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