STR720 datasheet(285/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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Bit 13

ERR: Error

This flag is set whenever one of the errors listed below has occurred:

NANS: No ANSwer. The timeout for a host response has expired.

CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the

token or in the data, was wrong.

BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID,

data, and/or CRC.

FVIO: Framing format Violation. A non-standard frame was received (EOP not

in the right place, wrong token sequence, etc.).

The USB software can usually ignore errors, since the USB Peripheral and the

PC host manage retransmission in case of errors in a fully transparent way. This

interrupt can be useful during the software development phase, or to monitor

the quality of transmission over the USB bus, to flag possible problems to the

user (e.g. loose connector, too noisy environment, broken conductor in the USB

cable and so on). This bit is read/write but only ‘0’ can be written and writing ‘1’

has no effect.

Bit 12

WKUP: Wake up

This bit is set to 1 by the hardware when, during suspend mode, activity is

detected that wakes up the USB Peripheral. This event asynchronously clears

the LP_MODE bit in the CTLR register and activates the USB_WAKEUP line,

which can be used to notify the rest of the device (e.g. wake-up unit) about the

start of the resume process. This bit is read/write but only ‘0’ can be written and

writing ‘1’ has no effect.

Bit 11

SUSP Suspend mode request

This bit is set by the hardware when no traffic has been received for 3mS,

indicating a suspend mode request from the USB bus. The suspend condition

check is enabled immediately after any USB reset and it is disabled by the

hardware when the suspend mode is active (FSUSP=1) until the end of resume

sequence. This bit is read/write but only ‘0’ can be written and writing ‘1’ has no

effect.

Bit 10

RESET: USB RESET request

Set when the USB Peripheral detects an active USB RESET signal at its inputs.

The USB Peripheral, in response to a RESET, just resets its internal protocol

state machine, generating an interrupt if RESETM enable bit in the USB_CNTR

cleared. All configuration registers do not reset: the microcontroller must

explicitly clear these registers (this is to ensure that the RESET interrupt can be

safely delivered, and any transaction immediately followed by a RESET can be

completed). The function address and endpoint registers are reset by an USB

reset event.

This bit is read/write but only ‘0’ can be written and writing ‘1’ has no effect.

STR720 数据表(PDF) 285 Page - STMicroelectronics

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