STR720 datasheet(283/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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USB Interrupt Status Register (USB_ISTR)

Address Offset: 44h

Reset Value: 0000 0000 0000 0000 (0000h)

This register contains the status of all the interrupt sources allowing application software to

determine, which events caused an interrupt request.

The upper part of this register contains single bits, each of them representing a specific event.

These bits are set by the hardware when the related event occurs; if the corresponding bit in

the USB_CNTR register is set, a generic interrupt request is generated. The interrupt routine,

examining each bit, will perform all necessary actions, and finally it will clear the serviced bits.

If any of them is not cleared, the interrupt is considered to be still pending, and the interrupt

line will be kept high again. If several bits are set simultaneously, only a single interrupt will be

generated.

Endpoint transaction completion can be handled in a different way to reduce interrupt

response latency. The CTR bit is set by the hardware as soon as an endpoint successfully

completes a transaction, generating a generic interrupt request if the corresponding bit in

USB_CNTR is set. An endpoint dedicated interrupt condition is activated independently from

the CTRM bit in the USB_CNTR register. Both interrupt conditions remain active until

software clears the pending bit in the corresponding USB_EPnR register (the CTR bit is

actually a read only bit). The USB Peripheral has two interrupt request lines:

•

Higher priority USB IRQ: The pending requests for endpoints, which have transactions

with a higher priority (isochronous and double-buffered bulk) and they cannot be masked.

•

Lower priority USB IRQ: All other interrupt conditions, which can either be non-maskable

pending requests related to the lower priority transactions and all other maskable events

flagged by the USB_ISTR high bytes.

For endpoint-related interrupts, the software can use the Direction of Transaction (DIR) and

EP_ID read-only bits to identify, which endpoint made the last interrupt request and called the

corresponding interrupt service routine.

The user can choose the relative priority of simultaneously pending USB_ISTR events by

specifying the order in which software checks USB_ISTR bits in an interrupt service routine.

Reserved

EP_ID[3:0]

rcrcrc

rcrc

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