STR720 datasheet(295/401 Pages) STMICROELECTRONICS

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STR720 - USB SLAVE INTERFACE (USB)

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Bit 6

DTOG_TX: Data Toggle, for transmission transfers

If the endpoint is non-isochronous, this bit contains the required value of the

data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted.

Hardware toggles this bit when the ACK handshake is received from the USB

host, following a data packet transmission. If the endpoint is defined as a

control one, hardware sets this bit to 1 at the reception of a SETUP PID

addressed to this endpoint.

If the endpoint is using the double buffer feature, this bit is used to support

packet buffer swapping too (Refer to Section “Double-Buffered Endpoints”)

If the endpoint is Isochronous, this bit is used to support packet buffer

swapping since no data toggling is used for this sort of endpoints and only

DATA0 packet are transmitted (Refer to section “Isochronous Transfers”).

Hardware toggles this bit just after the end of data packet transmission, since

no handshake is used for Isochronous transfers.

This bit can also be toggled by the software to initialize its value (mandatory

when the endpoint is not a control one) or to force a specific data toggle/

packet buffer usage. When the application software writes ‘0’, the value of

DTOG_TX remains unchanged, while writing ‘1’ makes the bit value toggle.

This bit is read/write but it can only be toggled by writing 1.

Bit 5:4

STAT_TX [1:0] Status bits, for transmission transfers

These bits contain the information about the endpoint status, listed in Table

65. These bits can be toggled by the software to initialize their value. When

the application software writes ‘0’, the value remains unchanged, while writing

‘1’ makes the bit value toggle. Hardware sets the STAT_TX bits to NAK, when

a correct transfer has occurred (CTR_TX=1) corresponding to a IN or SETUP

(control only) transaction addressed to this endpoint. It then waits for the

software to prepare the next set of data to be transmitted.

Double-buffered bulk endpoints implement a special transaction flow control,

which controls the status based on buffer availability condition (Refer to

Section “Double-Buffered Endpoints”).

If the endpoint is defined as Isochronous, its status can only be “VALID” or

“DISABLED”. Therefore, the hardware cannot change the status of the

endpoint after a successful transaction. If the software sets the STAT_TX bits

to ‘STALL’ or ‘NAK’ for an Isochronous endpoint, the USB Peripheral

behaviour is not defined. These bits are read/write but they can be only

toggled by writing ‘1’.

Bit 3:0

EA[3:0] Endpoint Address.

Software must write in this field the 4-bit address used to identify the

transactions directed to this endpoint. A value must be written before enabling

the corresponding endpoint.

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