STR720 datasheet(297/401 Pages) STMICROELECTRONICS

297 / 401 page

STR720 - USB SLAVE INTERFACE (USB)

297/401

19.6.3

Buffer Descriptor Table

Although this table is located inside packet buffer memory, its entries can be considered as

additional registers used to configure the location and size of packet buffers used to exchange

data between USB and the STR720. Due to the common APB bridge limitation on word

addressability, all packet memory locations are accessed by the APB using 32-bit aligned

addresses, instead of the actual memory location addresses utilized by the USB Peripheral for

the USB_BTABLE register and buffer description table locations. In the following pages two

location addresses are reported: the one to be used by application software while accessing

the packet memory, and the local one relative to USB Peripheral access. To obtain the correct

STR720 memory address value to be used in the application software while accessing the

packet memory, the actual memory location address must be multiplied by two. The first

packet memory location is located at 0xC000 8800.

The buffer description table entry associated with the USB_EPnR registers is described

below. A thorough explanation of packet buffers and buffer descriptor table usage can be

found in the Section “Structure and Usage of Packet Buffers”.

Transmission Buffer Address n (USB_ADDRn_TX)

Address Offset: [USB_BTABLE] + n*16

USB local Address: [USB_BTABLE] + n*8

765432

ADDRn_TX[15:1]

Bits 15:1

ADDRn_TX[15:1]. Transmission Buffer Address

These bits point to the starting address of the packet buffer containing data

to be transmitted by the endpoint associated with the USB_EPnR register

at the next IN token addressed to it.

Bit 0

Must always be written as ‘0’ since packet memory is word-wide and all

packet buffers must be word-aligned.

STR720 数据表(PDF) 297 Page - STMicroelectronics