STR720 datasheet(305/401 Pages) STMICROELECTRONICS

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STR720 - WATCHDOG TIMER (WDG)

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20.4 Register description

The Watchdog Timer registers can not be accessed by byte.

The reserved bits can not be written and they are always read at ‘0’.

WDT Control Register (WDTCR)

Address Offset: 00h

Reset value: 0000h

Bit 15:3 = Reserved.

Bit 2 = EE: EXT_CK Enable bit.

1: EXT_CK signal, (CLK_AF/8 is used as counting clock, its period must be at least 4 times

the APB_CLK period.

0: APB_CLK is used as counting clock.

This bit can be written as long as Watchdog mode is not entered (WE bit = 0). Once WE bit is

set to ‘1’, the value of EE cannot be changed anymore.

Bit 1 = SC: Start Counting bit.

1: the Prescaler loads the Prescaler pre-load value (WDTPR), the Counter loads the Timer

pre-load value (WDTVR) and starts counting

0: the Counter is stopped. To restart it, SC setting will generate a re-loading of the Prescaler

pre-load value and Timer pre-load value. These functionalities are permitted only in Timer

Mode (WE bit = 0).

Bit 0 = WE: Watchdog Enable bit.

1: Watchdog Mode is enabled

0: Timer Mode is enabled

This bit can’t be reset by software.

If the external WDGEN signal is high the WE bit is written to ‘1’ by hardware as soon the reset

has elapsed else can write to ‘1’ by software but cannot be cleared.

When WE bit is high, SC bit has no effect.

765432

reserved

-rw

STR720 数据表(PDF) 305 Page - STMicroelectronics