STR720 datasheet(304/401 Pages) STMICROELECTRONICS

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STR720 - WATCHDOG TIMER (WDG)

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When it reaches the end of count value (0000h) an End of Count interrupt is generated (EC)

and the WDTVR value is automatically re-loaded. The Counter runs until the SC bit is cleared.

Setting SC bit again, both the Counter and the Prescaler are re-loaded with the values

contained in registers WDTVR and WDTPR respectively, so it does not restart from where it

was eventually stopped, but from a defined situation without need to reset and re-program the

module. It is clear that, on the other hand, it is not possible to change on fly the prescaling

factor since it will only effect the counter after a restart command (SC bit setting which

generates a re-load operation).

The clock input signal can be either the APB_CLK or an alternate clock signal, having at least

a period four times longer than the period of the APB clock. This can allow for example to

generate time basis independent from the APB clock which could dynamically change

according to the system mode setting (run mode, low power mode, etc.). This alternate clock

signal is derived from the RTC clock and is equal to CLK_AF divided by 8.

20.3.2

Watchdog mode

If WE bit of WDTCR register is written to ‘1’ by software, the peripheral enter in Watchdog

mode. This operating mode can not be changed by software (the SC bit has no effect and WE

bit cannot be cleared).

As the peripheral enters in this operating mode, the WDTVR value is loaded in the Counter

and the Counter starts counting down. When it reaches the end of count value (0000h) a

system reset signal is generated (SYS RST).

If the sequence of two consecutive values A55Ah, 5AA5h is written in the WDTKR register

see Section 20.4, the WDTVR value is re-loaded in the Counter, so the end of count can be

avoided.

STR720 数据表(PDF) 304 Page - STMicroelectronics