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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 308 Page - STMicroelectronics |
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STR720 数据表(HTML) 308 Page - STMicroelectronics |
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308 / 401 page  STR720 - WATCHDOG TIMER (WDG) 308/401 WDT Key Register (WDTKR) Address Offset: 18h Reset value: 0000h Bit 15:0 = K[15:0]: Key Value. When Watchdog Mode is enabled, writing in this register the two consecutive values (A55Ah, 5AA5h) the Counter is initialized to TV[15:0] value and the Prescaler value in WTDPR register take effect. Any number of instructions can be executed between the two writes. If Watchdog Mode is disabled (WE = 0) a writing in this register has no effect. The reading value of this register is 0000h. 20.4.1 Register Map A summary of the WDG registers is given in the following table. Refer to Table 20 on page 49 for the base address. 15 14 13 12 11 10 9 8 765432 1 0 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Table 68. Watchdog Timer Peripheral Register Map Addr. Offset Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 WDTCR reserved EE SC WE 4 WDTPR reserved PR(7:0) 8 WDTVR TV(15:0) C WDTCNT CNT(15:0) 10 WDTSR reserved EC 14 WDTMR reserved MEC 18 WDTKR K[15:0] 1 |
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