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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 307 Page - STMicroelectronics |
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STR720 数据表(HTML) 307 Page - STMicroelectronics |
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307 / 401 page  STR720 - WATCHDOG TIMER (WDG) 307/401 WDT Counter Register (WDTCNT) Address Offset: 0Ch Reset value: FFFFh Bit 15:0 = CNT[15:0]: Timer Counter Value. The current counting value of the 16-bit Counter is available reading this register. WDT Status Register (WDTSR) Address Offset: 10h Reset value: 0000h Bit 15:1 = Reserved. Bit 0 = EC: End of Count pending bit. 1: the End of Count has occurred 0: no End of Count has occurred In Watchdog Mode (WE = 1) this bit has no effect. This bit can be set only by hardware and must be reset by software. WDT Mask Register (WDTMR) Address Offset: 14h Reset value: 0000h Bit15:1 = Reserved. Bit 0 = ECM: End of Count Mask bit. 1: End of Count interrupt request is enabled 0: End of Count interrupt request is disabled 15 14 13 12 11 10 9 8 765432 1 0 CNT15 CNT14 CNT13 CNT12 CNT11 CNT10 CNT9 CNT8 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 rrrrrr r r rrrrr r r r 15 14 13 12 11 10 9 8 765432 1 0 reserved EC -rc 15 14 13 12 11 10 9 8 765432 1 0 reserved ECM -rw 1 |
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