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STR720 数据表(PDF) 310 Page - STMicroelectronics |
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STR720 数据表(HTML) 310 Page - STMicroelectronics |
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310 / 401 page ![]() STR720 - EXTENDED FUNCTION TIMER (EFT) 310/401 21.3 Functional Description 21.3.1 Counter The principal block of the Programmable Timer is a 16-bit counter and its associated 16-bit registers. Writing in the Counter Register (CNTR) resets the counter to the FFFCh value. The timer clock source can be either internal or external selecting ECKEN bit of CR1 register. When ECKEN = 0, the frequency depends on the prescaler division bits (CC7-CC0) of the CR2 register. An overflow occurs when the counter rolls over from FFFFh to 0000h then the TOF bit of the SR register is set. An interrupt is generated if TOIE bit of the CR2 register is set; if this condition is false, the interrupt remains pending to be issued as soon as it becomes true. Clearing the overflow interrupt request is done by a write access to the SR register while the TOF bit is set with the data bus 13-bit at ‘0’, while all the other bits shall be written to ‘1’ (the SR register is clear only, so writing a ‘1’ in a bit has no effect: this makes possible to clear a pending bit without risking to clear a new coming interrupt request from another source). 1 |
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