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STR720 数据表(PDF) 325 Page - STMicroelectronics |
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STR720 数据表(HTML) 325 Page - STMicroelectronics |
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325 / 401 page ![]() STR720 - EXTENDED FUNCTION TIMER (EFT) 325/401 Note All formulas in this chapter assume that APB_CLK is the clock driving the EFT. If External clock (FEXT) is selected, replace (FAPB / TPRESC) by FEXT., where TPRESC = (CC7..CC0 + 1). 21.4 Register Description Each Timer is associated with two control and one status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter. Every register can have only an access by 16 bits, that means is not possible to read or write only a byte. Input Capture A Register (ICAR) Address Offset: 00h Reset value: xxxxh This is a 16-bit read only register that contains the counter value transferred by the Input Capture A event. Figure 55. Pulse Width Modulation Input Mode Timing 15 14 13 12 11 10 9 8 765432 1 0 MSB LSB rrrrrr r r rrrrr r r r COUNTER 34E2 0000 0001 2ED0 2ED1 2ED2 34E2 0000 ICAPA capture A capture B capture A 0002 PERIOD = ICAPA PULSE LENGTH = ICAPB Capture A, period measurement, reset counter Interrupt Capture B, pulse width measurement 1 |
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