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STR720 数据表(PDF) 329 Page - STMicroelectronics |
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STR720 数据表(HTML) 329 Page - STMicroelectronics |
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329 / 401 page ![]() STR720 - EXTENDED FUNCTION TIMER (EFT) 329/401 Control Register 2 (CR2) Address Offset: 18h Reset value: 0001h Bit 15 = ICAIE: Input Capture A Interrupt Enable 0: No interrupt on input capture A. 1: Generate interrupt if ICFA flag is set. Bit 14 = OCAIE: Output Compare A Interrupt Enable 0: No interrupt on OCFA set. 1: Generate interrupt if OCFA flag is set. Bit 13 = TOIE: Timer Overflow Interrupt Enable 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 12= ICBIE: Input Capture B Interrupt Enable 0: No interrupt on input capture B. 1: Generate interrupt if ICFB flag is set. Bit 11 = OCBIE: Output Compare B Interrupt Enable 0: No interrupt on OCFB set. 1: Generate interrupt if OCFB flag is set. Bit 10:8 = Reserved. These bits must be always written to 0. Bit 7:0 = CC7-CC0: Prescaler division factor This 7-bit string is the factor used by the prescaler to divide the internal clock. Timer clock will be equal to f APB / CC7÷CC0. 15 14 13 12 11 10 9 8 765432 1 0 ICAIE OCAIE TOE ICBIE OCBIE reserved CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 rw rw rw rw rw - rw rw rw rw rw rw rw rw 1 |
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