STR720 datasheet(333/401 Pages) STMICROELECTRONICS

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STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC)

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22.3.1

Normal (Round-Robin) Operation of ADC

In its normal mode of operation, the converter samples each input channel for 512 cycles of

the over-sampling clock. In the first clock cycle, the

Σ−∆ modulator is reset and the digital filter

cleared. The remaining 1-bit samples from the modulator are filtered by the Sinc3 filter and a

16 bit output sample supplied to the relevant data register after 512 clock cycles, the period

over which the Sinc3 filter has filled up and settled down. The channel select will then switch to

the next input channel, the reset will again be asserted on the first clock cycle, and the filter

will again fill up over 512 cycles to produce a sample. This process will be repeated for each

of the channels continually in a round-robin fashion.

22.3.2

Single-Channel Operation

When sampling a single channel, that channel alone will be selected as input to the analog

signal to the sigma-delta modulator. The functionality of the converter will remain the same as

above in that the converter will be reset every 512 cycles, once a valid sample is produced.

However, to maintain the same output frequency of the converter, only one of these samples

will be taken out of every four, thus a valid sample for the channel will be produced every 2048

oversampling clock cycles, as in normal operations.

22.3.3

Low-rate operating mode

In case the required sample rate is particularly low, a special decimation mode can be used to

overcome the limitation of prescaler configurations. This mode is selected by setting DEC bit

of ADCSR register. In this way the oversampling factor becomes 5120 instead of 512 and a

valid sample for a given channel will be produced each 20480 oversampling clock cycles,

instead of 2048.

22.3.4

Interrupt and DMA Requests

An active-high interrupt/DMA request flag will be set depending on the mode of operation.

In round-robin channel selection mode, the interrupt flag will be set when all data available

(DA) flags in the control register are set, and all the interrupt enables (IE) are also set. In this

way the interrupt/DMA request (depending on which function is currently enabled) will be

activated when all channels have been converted and their values are stored in the

corresponding data registers. The interrupt/DMA request is deasserted when all data

registers are read, this being the typical response of a DMA controller, or when “0” is written in

all DA bits of ADCCSR register, this last case being typical of an interrupt response routine. It

must be noticed that in order to work properly in this configuration all interrupt enable bits

need to be set.

In single channel mode, the interrupt flag will be set when the data available flag and the

interrupt flag for the selected channel are set. The interrupt request is deasserted by reading

the data register associated to the selected channel (DMA response) or writing “0” in the

corresponding DA bit of ADCCSR register (interrupt response). In order to have a proper

single-channel interrupt/DMA request, besides selecting the single-channel mode and

configuring which channel is to be converted using AXT and A[1:0] bits in ADCCSR register,

the corresponding interrupt enable bit needs to be set as well.

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