STR720 datasheet(330/401 Pages) STMICROELECTRONICS

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STR720 - EXTENDED FUNCTION TIMER (EFT)

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Status Register (SR)

Address Offset: 1Ch

Reset value: 0001h

Bit 15= ICFA: Input Capture Flag A

0: No input capture (reset value).

1: An input capture has occurred. To clear this bit, write the SR register, with a ‘0’ on the bit 15

(and ‘1’ in all the other bit, just to avoid an unwanted clearing of another pending bit).

Bit 14= OCFA: Output Compare Flag A

0: No match (reset value).

1: The content of the counter has matched the content of the OCAR register. This bit is not set

in the PWM mode even if counter matches OCAR. To clear this bit, write the SR register, with

a ‘0’ on the bit 14 (and ‘1’ in all the other bit, just to avoid an unwanted clearing of another

pending bit).

Bit 13= TOF: Timer Overflow

0: No timer overflow (reset value).

1:The counter rolled over from FFFFh to 0000h. To clear this bit, write the SR register, with a

‘0’ on the bit 13 (and ‘1’ in all the other bit, just to avoid an unwanted clearing of another

pending bit).

Bit 12= ICFB: Input Capture Flag B

0: No input capture (reset value).

1: An input capture has occurred.To clear this bit, write the SR register, with a ‘0’ on the bit 12

(and ‘1’ in all the other bit, just to avoid an unwanted clearing of another pending bit).

Bit 11= OCFB: Output Compare Flag B

0: No match (reset value).

1: The content of the counter has matched the content of the OCBR register. It is set in PWM

mode too. To clear this bit, write the SR register, with a ‘0’ on the bit 11 (and ‘1’ in all the other

bit, just to avoid an unwanted clearing of another pending bit).

765432

ICFA

OCFA

TOF

ICFB

OCFB

reserved

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