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H5GQ2H24AFR-R0C 数据表(PDF) 57 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 57 Page - Hynix Semiconductor |
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57 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 57 H5GQ2H24AFR 4.7. MODE REGISTER 6 (MR6) Mode Register 6 controls the WCK2CK alignment point and defines VREFD related features such as source, level, offsets, VREFD Merge and VREFD Auto Calibration mode, as shown in Figure 30. The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=1, BA2=1 and BA3=0. Figure 30. Mode Register 6 (MR6) Definition WCK2CK Alignment Point (WCKPIN) Bit A0 defines the position of the alignment point between CK and WCK. When set to ‘0‘, the alignment point will be at the phase detector inside the GDDR5 SGRAM. When set to ‘1‘, the alignment point will be at the CK and WCK pins. Input Reference Voltage for DQ and DBI# Pins GDDR5 SGRAMs offer multiple options for the input reference voltage (Vref) for the DQ and DBI# pins, as shown in Figure 31. A11 A10 A9 A8 VREFD Offset 00 00 0 / default 00 01 +1 00 10 +2 00 11 +3 01 00 +4 01 01 +5 01 10 +6 01 11 +7 10 00 0 / Auto (opt.) 10 01 ‐7 10 10 ‐6 10 11 ‐5 11 00 ‐4 11 01 ‐3 11 10 ‐2 11 11 ‐1 BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01 10 0 VREFD Offset Bytes in rows A‐F VREFD Offset Bytes in rows M‐U VREFD Auto VREFD VREFD Merge WCK PIN A3 VREFD 0external VREFD pins 1 internally generated A1 VREFD Merge 0Off 1On A7 A6 A5 A4 VREFD Offset 000 0 0 / default 000 1 +1 001 0 +2 001 1 +3 010 0 +4 010 1 +5 011 0 +6 011 1 +7 100 0 0 / Auto (opt.) 100 1 ‐7 101 0 ‐6 101 1 ‐5 110 0 ‐4 110 1 ‐3 111 0 ‐2 111 1 ‐1 A0 WCK2CK Alignment Pt. 0 PD inside DRAM 1PD at pins |
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