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H5GQ2H24AFR-R0C 数据表(PDF) 84 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 84 Page - Hynix Semiconductor |
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84 / 172 page ![]() This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 84 H5GQ2H24AFR •WSM: WRITE‐With‐Singlebyte‐Mask: 3 cycle command where the 1st cycle carries address information, the 2nd and 3rd cycle carry data mask information Figure 53. WRITE-With-Singlebyte-Mask Command CS# WE# CAS# RAS# CKE# A9 (A12) A1 A10,A11 A8 A7 LOW WSM CK CK# 0,1 BA0‐BA3 A2‐A5 A0,A6 DM DM DM DM DM DM DM DM EN AP DIS AP CA BA CA CA BA = Bank Address; CA = Column Address; DM = Data Mask EN AP = Enable Auto‐Precharge; DIS AP = Disable Auto‐Precharge DM DM DM DM DM DM DM DM Note: NOP shown as an example only |
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