H5GQ2H24AFR-R0C datasheet(38/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

3.5. WRITE TRAINING

Write training allows the memory controller to find the data‐eye center (symbol training) and burst frame

location (frame training) for each high‐speed input of the GDDR5 SGRAM. Each pin (DQ0‐DQ31, DBI0#‐

DBI3#) can be individually trained during this sequence.

For Write Training the following conditions must be true:

•at least one bank is active, or an auto refresh must be in progress and bit A2 in Mode Register 5 (MR5) is set to 0 to

allow training during auto refresh (to disable this special REF enabling of the WCK clock tree an ACT command

must be issued, or the device must be set into power‐down or self refresh mode)

•the PLL must be locked, if enabled.

•WCK2CK training should be complete

• Read training should be complete

•RDBI and WDBI must be enabled prior to and during Write Training if the training shall include the DBI# pins.

RDCRC and WRCRC must be enabled prior to and during Write Training if the training shall include the EDC

pins.

The following commands are associated with Write Training:

•WRTR to write a burst of data directly into the Read FIFO;

•RDTR to read a burst of data directly out of the Read FIFO.

Neither WRTR nor RDTR access the memory core. No MRS is required to enter Write Training.

Figure 16 shows an example of the internal data paths used with WRTR and RDTR. Figure 21 shows a typ‐

ical Write training command sequence using WRTR and RDTR. Table 14 lists AC timing parameters asso‐

ciated with WRITE Training.

Table 14 WRTR and RDTR Timings

PARAMETER

SYMBOL

VALUES

UNIT

NOTES

MIN

MAX

ACTIVE to WRTR command delay

tRCDWTR

–

ACTIVE to RDTR command delay

tRCDRTR

–

REFRESH to RDTR or WRTR command delay

tREFTR

–

RD/WR bank A to RD/WR bank B command delay

different bank groups

tCCDS

2–

tCK

tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive

WRTR commands.

WRTR to RDTR command delay

tWTRTR

WL+BL/4+1

-tWLmin

–tCK

WRITE to WRTR command delay

tWRWTR

WL+CRCWL+2

–

tCK

READ or RDTR to WRITE or WRTR command delay

tRTW

CL+BL/4+2‐WL

–

tCK

tRTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI

shall be considered in the calculation of the bus turnaround time.

tWTRTR is Internal WRTR to External RDTR command delay. (Figure 21).

In case, External WRTR to External RDTR command delay time is “WL+(WL+BL/4+1‐tWLmin)”.

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