H5GQ2H24AFR-R0C datasheet(83/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

Figure 52. WDM Timing

NOP

WDM

NOP

2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

WL = WLmrs = 2

Bank a,

Col m

CK#

COMMAND

DBI#

1. WLmrs = 2 is shown as an example. Actual supported values will be found in the MR and AC timings sections.

WCK#

WCK

3. EDC may be on or off. See Figure 4 for EDC Timing.

T3n

T4n

T5n

T2n

5. For WRITE operations it is important that the latching point meet the data valid window requirements, which may or may not be center aligned at the pins.

6. Before the WRITE commands, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDWR must be met.

Bank a,

Col n

DBI

m+7

tCCD

n+7

DBI

n+7

WL = WLmrs = 2

4. tCCD = tCCDS when bank groups is disabled or the second WRITE is to a different bank group, otherwise tCCD=tCCDL.

Notes:

7. tWCK2DQI = 0 is shown for illustration purposes.

DONʹT CARE

TRANSITIONING DATA

ADDRESS

DM m

DM n

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