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H5GQ2H24AFR-R0C 数据表(PDF) 9 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 9 Page - Hynix Semiconductor |
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9 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 9 H5GQ2H24AFR . Figure 2: Block Diagram of an example clock system Clock Phase Oscillator Q D CMD/ADD CMD/ADD DRAM Q D QB DQ [0]‐[7] D Q early/late Receiver D Q WCKint DQ DRAM PLL Q D D Q Phase detector/ corelogic early/late from For 8 data bits Controller GDDR5 SGRAM PLL clock Data Tx/Rx WCK/WCK# (2GHz) CK/CK# (1GHz) CMD sampled by CK/CK# as SDR ADD sampled by CK/CK# as DDR ADD/CMD centered with CK/CK# calibration data Phase accumulator Controller Clock Phase Controller (4Gbps) core core (1GHz) D Q WCK2CK Alignment To EDC pin /2 |
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