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H5GQ2H24AFR-R0C 数据表(PDF) 60 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 60 Page - Hynix Semiconductor |
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60 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 60 H5GQ2H24AFR 4.8. MODE REGISTER 7 (MR7) Mode Register 7 controls features like PLL Standby,Low Frequency mode, Auto Synchronization, Data Preamble, operation, Half VREFD, VDD Range and DCC as shown in Figure 32. The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=1 and BA3=0. Figure 32. Mode Register 7 (MR7) Definition PLL Standby When enabled by bit A0, the PLL is put into a standby mode upon entering self refresh even if the WCK clocks are disabled. The max. duration the PLL can be held in this standby state (tSTDBY) is given in the vendor‘s datasheet. Upon exiting self refresh WCK2CK training is required to e.g. set the data synchronizers, and the PLL will remain in the standby state until a PLL reset is issued, at which time the PLL will lock to the already stable WCK signal in a significantly shorter time than tLK. The standby lock time tSTDBYLK is to be defined in the vendor’s data sheet. If a normal lock is desired (e.g. if the frequency has changed) the PLL Standby bit will first have to be disabled before issuing PLL reset. A11 A10 DCC 00 no DCC / DCC off or hold / opt. 01 DCC start 10 DCC reset l 11 RFU A3 Low Frequency Mode 0Off 1On A4 WCK2CK Auto Sync 0Off 1On A5 Data Preamble 0Off 1On A6 0Off 1On A7 Half VFRED 00.7 * VDDQ 10.5 * VDDQ BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01 11 0 DCC RFU Half VREFD Temp Sense DQ PreA Auto Sync LF Mode RFU PLL Stdby A0 PLL Standby 0Off 1On |
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