H5GQ2H24AFR-R0C datasheet(51/172 Pages) HYNIX

51 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

H5GQ2H24AFR

WCK01 / WCK23 Inversion

Bits A2 and A3 control whether the internal phase of the WCK01 and WCK23 clock inputs after internal

divide‐by‐2 shall be inverted, corresponding to a 2 U.I. phase shift. The bits are used in conjunction with

WCK2CK training mode.

RDQS Mode

Bit A5 enables the RDQS mode of the GDDR5 SGRAM. In this mode the EDC pins will act as a READ

strobe (RDQS). No CRC is supported in RDQS mode, and all related bits in MR4 will be ignored. A

detailed description of the RDQS mode can be found in the section entitled OPERATION.

DRAM Info

Bits A6 and A7 enable the DRAM Info mode which is provided to output the Vendor ID, or the current

junction temperature.

The Vendor ID identifies the manufacturer of the GDDR5 SGRAM, and provides the die revision,

memory density and FIFO depth.

The Temperature Readout provides the SGRAM’s junction temperature. The on‐chip is enabled in

advance by bit A6 in MR7.

WCK Termination

Bits A8 and A9 define the termination value for the on‐die termination (ODT) for the WCK01, WCK01#,

WCK23 and WCK23# pins in combination with the driver strength setting.

The termination can be set to a value of ZQ/2 which is intended for a single loaded system, or ZQ which

is intended for double load configurations with two devices sharing the WCK clocks. The WCK

termination may also be turned off.

Bank Groups

Bit A11 enables the bank groups feature. With A11 set to ‘1’, the bank groups feature is enabled and

tCCDL is 3tCK.

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